1. Field of the Invention
This invention relates to integrated circuit structures and more particularly to improvements in an isolation slot formed in an integrated circuit structure to electrically isolate adjacent active devices in the structure.
2. Description of the Prior Art
Isolation slots are formed in a single crystal silicon substrate of an integrated circuit structure to electrically isolate adjacent active devices in the structure. The formation of such an isolation slot is generally described in Bondur et al U.S. Pat. No. 4,104,086. Generally, the slot is formed by etching the silicon substrate and then oxidizing the silicon walls of the slot to form an oxide layer which functions as the electrically insulating isolation material. The remainder of the slot is then filled with any convenient filler material, such as polysilicon or vapor deposited silicon dioxide, and the structure is then planarized.
The thickness of the sidewall oxide layer in the slot determines the value of the device capacitance to the substrate, e.g., the collector to substrate capacitance in a bipolar transistor. Therefore, it is desirable to provide a thick isolation oxide layer, e.g., greater than 3000 Angstroms.
However, it has been observed that a slot oxidation step, involving formation of an oxide thickness of as much as 3000-5000 Angstroms or more may, cause propagation of damages to the silicon substrate, such as dislocations. When such damage reaches the active area of adjacent transistors, the resultant potential for damage will have a noticeable effect on yield of dies from a wafer. For example, in bipolar transistor technology, damage to the substrate by formation of isolation oxidation on the sidewalls of an isolation slot can cause shorts between collectors and emitters, particularly when thick layers of isolation oxide are formed, i.e., 3000 Angstroms or more.
It has been proposed, in IBM Technical Disclosure Bulletin, Vol. 20, No. 8, January 1978, to reduce such stresses by reducing the oxide thickness and increasing the oxide temperature. However, reduction of the oxide thickness, while possibly reducing the stress, does not enhance the desired isolation characteristics of the slot.
It, therefore, would be desirable to form an isolation slot having a much thicker oxide layer to reduce the device capacitance without the occurrence of damage to the adjoining integrated circuit structure.